MINIMIZATION TECHNIQUES AND LOGIC GATES Minimization Techniques: Boolean postulates and laws – De-Morgan’s Theorem - Minimization of Boolean expressions - Minterm – Maxterm - Sum of Products (SOP) – Product of Sums (POS) – Karnaugh map Minimization – Don’t care conditions. Tabulation method. Logic Gates: AND, OR, NOT, NAND, NOR, Exclusive-OR and Exclusive- NOR

Half Adder – Full Adder – Half Subtractor – Full Subtractor –Multiplexer/ Demultiplexer – Decoder /Encoder – Parity checker – Parity generators – Code converters: Binary to Gray and Gray to binary- Magnitude Comparator.

Latches, Flip flops:SR, JK, T, D– Characteristic table and equation, Counters: Synchronous counters, up/down counter, Modulo–n counter, Decade counters

Register, Shift registers-SISO, SIPO, PISO, PIPO, Classification of sequential circuits: Moore and Mealy, Design of synchronous sequential circuits, State diagram, State table, State minimization, State assignment, Introduction to Hazards: Static, Dynamic.

Memories: ROM, PROM, EEPROM, RAM, Programmable Logic Devices: Programmable Logic Array (PLA), Programmable Array Logic (PAL), Implementation of combinational logic using Verilog HDL