Connected successfully Resource Link || SNS Courseware
Subject Details
Dept     : ECE
Sem      : 5
Regul    : 2019
Faculty : Dr.V.S.Nishok
phone  : 6381009983
E-mail  : nishok.vs.ece@snsct.org
206
Page views
38
Files
18
Videos
15
R.Links

Icon
Assignments

Due Date Is Over
Due Date: 17-09-2024
Implement the given Boolean expression using
1. Y = (A+(B.C))' and Y = ((A+B).(C+D))' using Static CMOS logic. [Reg no. 53 to 63] 2. Y = (A+(B.C))' and Y = ((A+B).(C+D))' using Pseudo NMOS logic. [Reg no. 64 to 74] 3. Three input NAND and NOR gate using Dynamic CMOS logic. [Reg no. 75 to 85] 4. Two input AND and OR gate using Domino CMOS logic. [Reg no. 86 to 96] 5. Y = (A+(B.C))' and Y = ((A+B).(C+D))' using Dynamic CMOS logic. [Reg no. 097 to 518]. Answers should be written in A4 sheet and the Assignment marks will be provided as per IQAC format.
Due Date Is Over
Due Date: 28-10-2024
Assignment II
1. Discuss in detail the Static latches and registers. [Reg no. 53 to 63] 2. Pipelining in sequential circuits. [Reg no. 64 to 74] 3. Explain the different types of power dissipation in VLSI circuits. [Reg no. 75 to 85] 4. Discuss briefly about low power design principles. [Reg no. 86 to 96] 5. Explain fault model and design for testability. [Reg no. 097 to 518]. Answers should be written in A4 sheet and the Assignment marks will be provided as per IQAC format.