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Dept     : ECE
Sem      : 5
Regul    : 2019
Faculty : Dr.V.S.Nishok
phone  : 6381009983
E-mail  : nishok.vs.ece@snsct.org
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  • Assignment

    Assignment topic is Assignment II and due date is 28-10-2024.

  • Lecture Notes

    Dear Students the Lecture Notes has been uploaded for the following topics:</br>Static and Dynamic Latches and Registers, </br>Timing issues, </br>Pipelines, </br>Clock strategies, </br>Low power memory circuits, </br>Synchronous design and Asynchronous, </br>Manufacturing test principles, </br>VLSI testing -need for testing, </br>Design strategies for test, </br>BIST, </br>Chip level and system level test techniques

  • Assignment

    Assignment topic is Implement the given Boolean expression using CMOS logic. and due date is 17-09-2024.

  • Question Bank

    Dear Students the Question Bank has been uploaded for the following topics:</br>Sequential logic design

  • Resource Link

    Dear Students the Resource Link has been uploaded for the following topics:</br>MOS Transistor Basics</br>Digital Basics</br>VERILOG LANGUAGE</br>Basic VLSI Design</br>Opensource VLSI tools</br>CMOS</br>VLSI Questions</br>VLSI Resources</br>VLSI Technology</br>VLSI Physical Design</br>Digital VLSI Testing</br>CMOS VLSI Design</br>Advanced VLSI Design

  • Youtube Video

    Dear Students the Youtube Video has been uploaded for the following topics:</br>INTRODUCTION TO VLSI DESIGN</br>VLSI Design Styles</br>VERILOG LANGUAGE</br>VLSI DESIGN FLOW</br>MOS Transistor Basics</br>CMOS Digital VLSI Design</br>CMOS Inverter Basics</br>Combinational Logic Design</br>Sequential Logic Design</br>Concept of Memory and its Designing</br>Introduction to HDL</br>Simulation, Synthesis and Design methodology in Verilog</br>Test Bench writing in Verilog</br>Practice-Set Verilog</br>Introduction to Stick Diagram</br>Design Rule Check</br>What is JTAG and Boundary Scan?</br>Timing Diagrams

  • Puzzles

    Dear Students the Puzzles has been uploaded for the following topics:</br>Basic MOS transistors, </br>CMOS fabrication – p-well process, </br>Basic VLSI

  • Lecture Notes

    Dear Students the Lecture Notes has been uploaded for the following topics:</br>Basic concepts- identifiers, </br>gate primitives, gate delays, </br>operators, timing controls, </br>procedural assignments conditional statements, </br>Design hierarchies, Behavioral and RTL modeling, </br>Test benches, Examples

  • Question Bank

    Dear Students the Question Bank has been uploaded for the following topics:</br>MOS TRANSISTOR PRINCIPLEs, </br>COMBINATIONAL LOGIC CIRCUITS

  • Lecture Notes

    Dear Students the Lecture Notes has been uploaded for the following topics:</br>n-well process, </br>CMOS fabrication – p-well process, </br>twin-tub process, </br>MOS transistor theory-IV characteristics, </br>CV characteristics, </br>Non-ideal IV effects, </br>DC characteristics, </br>Stick diagram, </br>Layout diagrams, </br>Examples of Combinational Logic Design, </br>Pass transistor Logic, Transmission gates, </br>Pseudo NMOS logic, Domino Logic, </br>Static and dynamic CMOS design, </br>Power dissipation, </br>Low power design principles