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Subject Details
Dept     : ECE
Sem      : 5
Regul    : 2019
Faculty : Dr.V.S.Nishok
phone  : 6381009983
E-mail  : nishok.vs.ece@snsct.org
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Lecture Notes

UNIT 1:
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n-well process
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CMOS fabrication – p-well process
pdf
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twin-tub process
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MOS transistor theory-IV characteristics
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CV characteristics
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Non-ideal IV effects
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DC characteristics
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Stick diagram
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Layout diagrams
UNIT 2:
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Examples of Combinational Logic Design
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Pass transistor Logic, Transmission gates
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Pseudo NMOS logic, Domino Logic
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Static and dynamic CMOS design
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Power dissipation
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Low power design principles
UNIT 3:
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Static and Dynamic Latches and Registers
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Timing issues
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Pipelines
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Clock strategies
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Low power memory circuits
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Synchronous design and Asynchronous
UNIT 4:
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Manufacturing test principles
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VLSI testing -need for testing
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Design strategies for test
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BIST
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Chip level and system level test techniques
UNIT 5:
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Basic concepts- identifiers
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gate primitives, gate delays
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operators, timing controls
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procedural assignments conditional statements
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Design hierarchies, Behavioral and RTL modeling
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Test benches, Examples