Connected successfully Announcements || SNS Courseware
Menu
Subject Details
Dept     : ECE
Sem      : 5
Regul    : R19
Faculty : Mr.J.Prabakaran
phone  : 9551144859
E-mail  : prabakaran.j.ece@snsct.org
456
Page views
63
Files
3
Videos
0
R.Links

Icon
Announcements

  • Lecture Notes

    Dear Students the Lecture Notes has been uploaded for the following topics:</br> CMOS fabrication- p-well process, </br> n-well process, </br> Twin-tub process, </br> MOS transistor theory , IV characteristics,, </br> Non-ideal IV effects, </br>CV characteristics, </br> CMOS inverter –DC characteristics, </br> Stick diagram, </br> Layout diagrams, </br>Examples of Combinational Logic Design, </br> Pass transistor Logic & Transmission gates, </br> Pseudo NMOS logic, </br> Static CMOS design, </br> dynamic CMOS design, </br> Domino Logic, </br> CMOS fabrication- p-well process, </br> Power dissipation, </br> Low power design principles

  • Question Bank

    Dear Students the Question Bank has been uploaded for the following topics:</br>unit-1 two marks, </br>unit-2 two marks, </br>unit-3 two marks, </br>unit-4 two marks, </br>unit-5 two marks

  • Youtube Video

    Dear Students the Youtube Video has been uploaded for the following topics:</br>Introduction of VLSI design</br>MOS Transistor principles</br>VLSI Design flow

  • Lecture Notes

    Dear Students the Lecture Notes has been uploaded for the following topics:</br>Static and Dynamic Latches and Registers, </br>Timing issues, </br>Pipelines, </br>Clock strategies, </br>Low power memory circuits, </br>Synchronous design., </br>Asynchronous design

  • Lecture Notes

    Dear Students the Lecture Notes has been uploaded for the following topics:</br>THEORY VLSI testing, </br>THEORY VLSI testing, </br>need for testing, </br>manufacturing test principles, </br>design strategies for test, </br>BIST, </br>chip level and system level test techniques, </br>THEORY Basic concepts, </br>identifiers, </br>gate primitives, </br>gate delays, </br>operators, timing controls, </br>procedural assignments conditional statements, </br>Design hierarchies, Behavioral and RTL modeling, </br>Test benches&Examples