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Subject Details
Dept     : ECE
Sem      : 5
Regul    : 2019
Faculty : Dr.V.S.Nishok
phone  : 6381009983
E-mail  : nishok.vs.ece@snsct.org
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Reference videos
INTRODUCTION TO VLSI DESIGN
VLSI Design Styles
VERILOG LANGUAGE
VLSI DESIGN FLOW
MOS Transistor Basics
CMOS Digital VLSI Design
CMOS Inverter Basics
Combinational Logic Design
Sequential Logic Design
Concept of Memory and its Designing
What is JTAG and Boundary Scan?
Tutorial Videos
Introduction to HDL
Simulation, Synthesis and Design methodology in Verilog
Test Bench writing in Verilog
Practice-Set Verilog
Introduction to Stick Diagram
Design Rule Check
Timing Diagrams
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