Subject Details
Dept     : ECE
Sem      : 5
Regul    : 2019
Faculty : m.pradeepa
phone  : NIL
E-mail  : pradeepa.m.ece@snsct.org
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Lecture Notes

UNIT 1:
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Non-ideal IV effects
pdf
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CMOS inverter –DC characteristics
pdf
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LAYOUT DIAGRAM
pdf
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CMOS fabrication- p-well process
pdf
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Stick diagram
pdf
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n-well process
pdf
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Twin-tub process
pdf
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MOS transistor theory , IV characteristics,
pdf
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CV characteristics
UNIT 2:
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Static CMOS design
pdf
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Power dissipation
pdf
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Pseudo NMOS logic
pdf
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Pass transistor Logic & Transmission gates
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Power dissipation
pdf
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Low power design principles
pdf
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Static CMOS design
pdf
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Examples of Combinational Logic Design
pdf
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Domino Logic
UNIT 3:
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Pipelines
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Timing issues
pdf
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Clock strategies
pdf
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Low power memory circuits
pdf
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Synchronous design
pdf
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Asynchronous design
pdf
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Static and Dynamic Latches and Registers
UNIT 4:
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Manufacturing test principles
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Design strategies for test
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BIST
pdf
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Chip level test techniques
UNIT 5:
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Basic concepts identifiers
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Gate primitives & gate delays
pdf
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Operators and timing controls
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Procedural assignments
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Design hierarchies
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Design hierarchies
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Behavioral and RTL modeling and Test benches
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Examples: decoder, equality detector, comparator