Subject Details
Dept     : CSE
Sem      : 3
Regul    : 2023
Faculty : vanitha G
phone  : 948621790
E-mail  : vanitha.g.cse@snsct.org
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Lecture Notes

UNIT 1:
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Instruction and Instruction sequencing
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Functional units – Basic operational concepts
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Assembly language
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Bus Structures – Performance
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Addressing modes
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Memory locations and address, Memory operations
UNIT 2:
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Design of fast adders – Half adder
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Addition and subtraction of signed numbers
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Design of fast adders – Full adder
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Design of fast adders – Half adder
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Multiplication of positive numbers
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Signed operand multiplication
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Signed operand multiplication
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Fast multiplication - Bit-Pair Recoding of Multipliers
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Fast multiplication - Bit-Pair Recoding of Multipliers
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Fast multiplication - Bit-Pair Recoding of Multipliers
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Integer Division - Restoring Division Algorithm
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Integer Division - Restoring Division Algorithm
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Integer Division - Non restoring Division Algorithm
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Integer Division - Non restoring Division Algorithm
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Floating point numbers and operations
UNIT 3:
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PROCESSOR AND PIPELINING
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Micro programmed control
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Hardwired control
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Pipelining: Basic concepts
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Data hazards , Instruction hazards
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Influence on Instruction sets , Data path and control consideration
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Case study : Processor Families
UNIT 4:
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MEMORY SYSTEM
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Basic concepts of Semiconductor RAMs
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ROMs – Speed, Size and Cost
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Cache memories
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Virtual memory
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Secondary storage
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Performance consideration
UNIT 5:
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I/O ORGANIZATION AND PARALLELISM
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Accessing I/O devices
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Interrupts
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Direct Memory Access
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Buses
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Instruction Level Parallelism
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Concepts and Challenges
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Introduction to Graphics Processing Units
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Buses