UNIT 1:
Boolean Algebra and Theorems
Boolean expression - Minimization of Boolean expressions
Minterm – Maxterm - Sum of Products (SOP) – Product of Sums (POS)
Karnaugh map Minimization
Quine - Mc Cluskey method of minimization
Logic gates and Implementations
UNIT 2:
Design procedure – Half adder
Parity checker - Parity generators
UNIT 3:
Latches, Edge triggered Flip flops SR, JK, T, D and Master slave
Synchronous/Asynchronous counters
UNIT 4:
Register, shift registers
Classification of sequential circuits: Moore and Mealy
Design of synchronous sequential circuits: state diagram, State table
State minimization - State assignment
Introduction to Hazards: Static, Dynamic
UNIT 5:
Memories: ROM, PROM, EEPROM, RAM, SRAM & DRAM
Programmable Logic Devices: Programmable Logic Array (PLA)
Programmable Array Logic (PAL)
Implementation of combinational logic using PROM and PLA
Implementation of combinational logic using PAL
Digital logic families: TTL, ECL and CMOS
